An instruction to be executed by a processor may be associated with a number of different operations. For example, execution of an instruction might involve: fetching the instruction; decoding the instruction; performing an Arithmetic-Logic Unit (ALU) operation; and accessing data/memory. The processor could perform all of these operations for one instruction before beginning any of the operations for the next instruction. This approach, however, may limit the rate at which the processor executes instructions.
It is known that processor performance may be improved when instructions are executed via a processor “pipeline.” FIG. 1 is a block diagram of a processor pipeline 100 including a fetch stage 110 that may retrieve an instruction from memory and increment a program counter. A decode stage 120 may translate that instruction and retrieve an operand, and an ALU stage 130 may perform arithmetic and logic operations on the operand. A data/memory stage 140 may read and/or write information as appropriate.
Note that each stage in the pipeline 100 may simultaneously perform operations associated with different instructions. For example, the fetch stage 110 may retrieve a first instruction from memory during a first clock cycle. When that operation is complete, the decode stage 120 may decode the first instruction and retrieve an operand during a second clock cycle. While the decode stage 120 is performing these operations for the first instruction, the fetch stage 110 may retrieve the next instruction from memory. Because the pipeline 100 performs operations associated with a number of different instructions at the same time, the rate at which the instructions are executed may be increased.